In circuit structure fabrication, there is a desire to continually increase densities of devices within a given chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration has led to a continued shrinking of circuit dimensions and device features. The ability to reduce the size of such features is driven by performance enhancements in the lithographic processes by which integrated circuit structures are formed on a wafer. This process is also referred to as photolithography, or simply lithography. As is well known, lithographic processes can be used to transfer a pattern of a photomask to a wafer. Consequently, feature size, line width, and the separation between features and lines are becoming increasingly smaller. Yield is affected by factors such as mask pattern fidelity, optical proximity effects, and photoresist processing. However, existing processes can result in undesirable effects that often times must be countered by either changing the design specification (to increase critical dimension or pitch, as examples) or using additional material, such as additional hardmask layers to protect underlying layers.